Parallel Design of a Batch-type Time-true ATM-network Simulator - Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conf

This paper presents the parallel design of a new type ATM network simulator. The proposed parallel design is to organize data by Virtual Paths and then to distribute them among processors, which all execute the same bunch of instructions on these data. The simulator is a pure time-true simulator but it is not a call-by-call type. It is characterized as a batch type. The whole duration of simulation time is divided into short time intervals of equal duration T. During T, a batch processing of events is executed and the time-points of the events are sorted. The number of sorting executions is drastically reduced in comparison to call-by-call simulator, achieving considerable timesaving. Besides, the data structure of the simulator is not only well fitted to parallel processing techniques, for hrther savings of execution time, but is appropriate for its implementation by a general purpose programming language.